The invention relates generally to fabrication of a semiconductor device and, more particularly, to a method of fabricating an isolation layer in a semiconductor device.
As the degree of integration of semiconductor devices has increased and the design rule has been reduced, pattern sizes of the semiconductor devices have been miniaturized. Particularly, as device sizes have been reduced to 40 nm technology or below, the importance of an isolation process that adjusts data retention time of semiconductor memory devices, e.g. dynamic random access memory (DRAM) devices to enhance a yield of the device has greatly increased. To enhance the data retention time of semiconductor devices, various process materials for the isolation method have been studied.
Among such isolation methods, a method for fabricating an isolation layer using a shallow trench isolation (STI) process, which has an excellent isolation property, is generally employed. In the STI process, the isolation layer is made by forming a trench with a predetermined depth in a semiconductor substrate and filling the trench with an insulation layer, followed by planarization. Meanwhile, as a critical dimension of the trench is decreased and a depth of the trench is increased with reduction in the device, the importance of selection of material for filling the trench is greatly increased. As the material for filling the trench to form the isolation layer, an oxide layer formed by a high density plasma (HDP) process is commonly employed. However, with the reduction in device sizes to 40 nm technology or less, a limitation in filling of the trench with the oxide layer by the HDP process has been exhibited. Accordingly, a method of filling the trench using a flowable insulation layer formed of a compound in which solvent and solute are mixed has been studied and employed. However, when filling the trench with the flowable insulation layer, various problems are generated according to the stress or shrinkage level of the flowable insulation layer and it is thus difficult to form a high quality insulation layer.
FIGS. 1A and 1B illustrate the problems generated when filling the trench with the flowable insulation layer according to prior practice.
Referring to FIGS. 1A and 1B, when filling the trench formed in a semiconductor substrate 100 with a flowable insulation layer 105, rapid variation in stress occurs in the flowable insulation layer by a subsequent process and this can result in delamination or formation of a crack 110 in the flowable insulation layer 105, particularly in a peripheral region. Also, in a subsequent process after filling the trench with the flowable insulation layer, the flowable insulation layer is shrunk to generate a slip or dislocation 115 (FIG. 1b). A pad layer 120 overlies the region of the slip or dislocation 115.) When these defects are generated, it is difficult to form a uniform, high quality insulation layer.
Accordingly, there is a need for a method for forming an isolation layer capable of ensuring stable device properties and high quality devices.